CPU DB

MIPS R5000

200.0 MHz

Specifications
Designer MIPS
Family R5000
Model
Code Name
Clock [MHz] 200.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V] 3.30
TDP [W]
Die Size [mm²] 84
Transistor [M] 3.6
Architecture
Data Path Width 64
Cores per Chip 1
Threads per Core 1
Microarchitecture
µarch R5000
ISA
FP Pipe Stages
Int Pipe Stages 5
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 32
L1 Data Cache 32
L2 Cache
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache 2048
L3 Cache
Process Technology
Fabricated By IDT
Process http://cpudb.stanford.edu/technologies/50
Technology CMOS
Feature Size [μm] 0.35
Channel Length [μm] 0.35
Metal Layers 3
Metal Type aluminum
FO4 Delay [ps] 126.0

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