CPU DB

DEC EV7 µarch

Microarchitecture
µarch EV7
ISA Alpha
FP Pipe Stages 7
Int Pipe Stages 7
Additional Specifications
ISA Extensions
Max µops (per-cycle) 6
IFU 4
LSFU 2
FPFU 2
TFU 6
Max Inst. Decoded 4
ROB Size 80
Inst. Window 35
IF Queue 4
Additional Specifications
BHT Size 29696
BTB Size 4096
BP Acc 0
Registers (INT) 39
Registers (FP) 31
Registers (All)
Memory BW [MB/s]
Out of Order true
Integrated Memory Ctrl

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
DEC Alpha 21364 EV7 EV7 2002-01-01 1792 1.50 0.18 36.0 1000.0 125.0 689.0 975.0 details
DEC Alpha 21364 EV7 EV7 2002-01-01 1536 1.50 0.18 36.0 1150.0 125.0 798.3 1130.7 details