Intel Merced µarch
| Microarchitecture |
| µarch |
Merced |
| ISA |
IA-64 |
| FP Pipe Stages |
8 |
| Int Pipe Stages |
8 |
|
Additional Specifications
|
| ISA Extensions |
|
| Max µops (per-cycle) |
11 |
| IFU |
2 |
| LSFU |
4 |
| FPFU |
2 |
| TFU |
11 |
| Max Inst. Decoded |
6 |
| ROB Size |
|
| Inst. Window |
6 |
| IF Queue |
24 |
|
Additional Specifications
|
| BHT Size |
20000 |
| BTB Size |
64 |
| BP Acc |
|
| Registers (INT) |
6400 |
| Registers (FP) |
128 |
| Registers (All) |
|
| Memory BW [MB/s] |
|
| Out of Order |
|
| Integrated Memory Ctrl |
|
| Designer |
Family |
Code Name |
Model |
μarch |
Released |
Cache |
Vdd |
Feature Size |
FO4 |
Clock |
TDP |
SPECInt 1992 |
SPECFp 1992 |
SPECInt 1995 |
SPECFp 1995 |
SPECInt 2000 |
SPECFp 2000 |
SPECInt 2006 |
SPECFp 2006 |
|
| Intel |
Itanium
|
Merced
|
|
Merced
|
|
96 |
|
0.18 |
46.8
|
733.0 |
|
|
|
|
|
|
576.6 |
|
|
details |
| Intel |
Itanium
|
Merced
|
|
Merced
|
2001-05-01 |
96 |
1.65 |
0.18 |
46.8
|
800.0 |
130.0 |
|
|
|
|
347.4 |
625.1 |
|
|
details |