Intel P6:Banias µarch

Microarchitecture
µarch P6:Banias
ISA x86-32
FP Pipe Stages
Int Pipe Stages
Additional Specifications
ISA Extensions SSE2
Max µops (per-cycle) 5
IFU 2
LSFU 3
FPFU 2
TFU 5
Max Inst. Decoded 3
ROB Size 40
Inst. Window
IF Queue
Additional Specifications
BHT Size
BTB Size
BP Acc
Registers (INT) 40
Registers (FP) 40
Registers (All) 40
Memory BW [MB/s]
Out of Order true
Integrated Memory Ctrl false

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
Intel Pentium M Dothan 760 P6:Banias 2048 0.09 19.1 2000.0 details
Intel Pentium M Banias P6:Banias 1024 1.17 0.13 25.2 1300.0 22.0 details
Intel Pentium M Banias P6:Banias 1024 0.92 0.13 25.2 900.0 7.0 details