CPU DB

Intel P5 µarch

Microarchitecture
µarch P5
ISA x86-32
FP Pipe Stages 6
Int Pipe Stages 5
Additional Specifications
ISA Extensions MMX
Max µops (per-cycle) 2
IFU 2
LSFU
FPFU 1
TFU 3
Max Inst. Decoded
ROB Size
Inst. Window
IF Queue
Additional Specifications
BHT Size
BTB Size 256
BP Acc
Registers (INT) 40
Registers (FP)
Registers (All)
Memory BW [MB/s]
Out of Order false
Integrated Memory Ctrl true

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
Intel Pentium P5 P5 1993-03-01 16 5.00 0.8 288.0 60.0 13.0 63.7 48.3 details
Intel Pentium P5 P5 1993-03-01 16 5.00 0.8 288.0 66.0 13.0 70.7 details
Intel Pentium MMX P55C P5 1997-01-01 32 2.80 0.28 100.8 200.0 7.3 details
Intel Pentium MMX P55C P5 1997-06-01 32 2.80 0.28 100.8 233.0 7.9 details
Intel Pentium P5 1994-07-01 16 3.37 0.6 216.0 100.0 3.9 113.5 80.7 3.2 2.1 details
Intel Pentium P5 1995-03-01 16 3.50 0.6 216.0 120.0 5.1 140.3 94.3 3.6 2.2 details
Intel Pentium N/A P5 16 3.37 0.6 216.0 75.0 81.9 59.7 2.4 1.5 details
Intel Pentium N/A P5 16 3.37 0.6 216.0 90.0 92.8 70.4 2.9 1.8 details
Intel Pentium P5 1995-06-01 16 2.48 0.35 90.0 133.0 4.3 169.5 104.7 4.0 2.5 details
Intel Pentium P5 256 2.48 0.35 90.0 150.0 31.7 details
Intel Pentium P5 1996-06-01 512 2.80 0.35 90.0 166.0 13.1 details
Intel Pentium N/A P5 512 2.80 0.25 72.0 233.0 17.0 7.1 4.4 details
Intel Pentium N/A P5 1996-06-01 512 2.80 0.25 72.0 200.0 15.7 details