| Microarchitecture | |
|---|---|
| µarch | PowerPC 7xx |
| ISA | |
| FP Pipe Stages | 6 |
| Int Pipe Stages | 4 |
| Additional Specifications | |
|---|---|
| ISA Extensions | |
| Max µops (per-cycle) | 2 |
| IFU | 2 |
| LSFU | 1 |
| FPFU | 1 |
| TFU | 4 |
| Max Inst. Decoded | 2 |
| ROB Size | 6 |
| Inst. Window | 5 |
| IF Queue | 6 |
| Additional Specifications | |
|---|---|
| BHT Size | 512 |
| BTB Size | 64 |
| BP Acc | |
| Registers (INT) | 32 |
| Registers (FP) | 32 |
| Registers (All) | |
| Memory BW [MB/s] | |
| Out of Order | true |
| Integrated Memory Ctrl | |
| Designer | Family | Code Name | Model | μarch | Released | Cache | Vdd | Feature Size | FO4 | Clock | TDP | SPECInt 1992 | SPECFp 1992 | SPECInt 1995 | SPECFp 1995 | SPECInt 2000 | SPECFp 2000 | SPECInt 2006 | SPECFp 2006 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IBM | PowerPC 7xx | Arthur | 740 | PowerPC 7xx | 1997-08-01 | 64 | 2.60 | 0.26 | 93.6 | 266.0 | 8.0 | details | ||||||||
| IBM | PowerPC 7xx | Arthur | 750 | PowerPC 7xx | 1998-10-01 | 64 | 2.60 | 0.26 | 93.6 | 400.0 | 8.0 | details |