Specifications | |
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Designer | IBM |
Family | PowerPC 7xx |
Model | 750 |
Code Name | Arthur |
Clock [MHz] | 400.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
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Voltage (Nom.) [V] | 2.60 |
TDP [W] | 8.0 |
Die Size [mm²] | 67 |
Transistor [M] | 6.35 |
Architecture | |
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Data Path Width | 32 |
Cores per Chip | 1 |
Threads per Core | 1 |
Microarchitecture | |
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µarch | PowerPC 7xx |
ISA | |
FP Pipe Stages | 6 |
Int Pipe Stages | 4 |
Cache (on-chip) | |
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L1 Unified Cache | |
L1 Instruction Cache | 32 |
L1 Data Cache | 32 |
L2 Cache | |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |
Process Technology | |
---|---|
Fabricated By | IBM |
Process | http://cpudb.stanford.edu/technologies/47 |
Technology | CMOS |
Feature Size [μm] | 0.26 |
Channel Length [μm] | 0.18 |
Metal Layers | 5 |
Metal Type | |
FO4 Delay [ps] | 93.6 |