CPU DB

Intel Sandy Bridge µarch

Microarchitecture
µarch Sandy Bridge
ISA x86-64
FP Pipe Stages
Int Pipe Stages
Additional Specifications
ISA Extensions SSE4.2 AVX
Max µops (per-cycle) 6
IFU 3
LSFU 3
FPFU 3
TFU 5
Max Inst. Decoded 6
ROB Size 168
Inst. Window
IF Queue
Additional Specifications
BHT Size
BTB Size
BP Acc
Registers (INT)
Registers (FP)
Registers (All)
Memory BW [MB/s]
Out of Order true
Integrated Memory Ctrl true

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
Intel Core i7 Sandy Bridge 2600 Sandy Bridge 2011-01-09 8192 0.032 6.5 3800.0 95.0 details