| Microarchitecture | |
|---|---|
| µarch | R10000 |
| ISA | |
| FP Pipe Stages | 7 |
| Int Pipe Stages | 5 |
| Additional Specifications | |
|---|---|
| ISA Extensions | |
| Max µops (per-cycle) | 5 |
| IFU | 2 |
| LSFU | 1 |
| FPFU | 3 |
| TFU | 6 |
| Max Inst. Decoded | 4 |
| ROB Size | 32 |
| Inst. Window | 5 |
| IF Queue | |
| Additional Specifications | |
|---|---|
| BHT Size | 512 |
| BTB Size | 512 |
| BP Acc | |
| Registers (INT) | 32 |
| Registers (FP) | 32 |
| Registers (All) | 64 |
| Memory BW [MB/s] | 3200 |
| Out of Order | true |
| Integrated Memory Ctrl | false |
| Designer | Family | Code Name | Model | μarch | Released | Cache | Vdd | Feature Size | FO4 | Clock | TDP | SPECInt 1992 | SPECFp 1992 | SPECInt 1995 | SPECFp 1995 | SPECInt 2000 | SPECFp 2000 | SPECInt 2006 | SPECFp 2006 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MIPS | R10000 | T5 | R10000 | 1996-01-01 | 64 | 3.30 | 0.35 | 126.0 | 180.0 | 9.3 | details | |||||||||
| MIPS | R10000 | T5 | R10000 | 1996-01-01 | 64 | 3.30 | 0.35 | 126.0 | 195.0 | 9.4 | 14.0 | details | ||||||||
| MIPS | R10000 | T5 | R10000 | 1996-01-01 | 64 | 3.30 | 0.35 | 126.0 | 196.0 | 9.7 | 8.4 | details | ||||||||
| MIPS | R10000 | T5 | R10000 | 1996-01-01 | 64 | 3.30 | 0.35 | 126.0 | 200.0 | 10.4 | details | |||||||||
| MIPS | R10000 | T5 | R10000 | 1996-01-01 | 64 | 3.30 | 0.35 | 126.0 | 250.0 | 13.5 | 16.8 | details |