CPU DB

MIPS R10000

T5, 200.0 MHz

Specifications
Designer MIPS
Family R10000
Model
Code Name T5
Clock [MHz] 200.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V] 3.30
TDP [W]
Die Size [mm²] 298
Transistor [M] 6.8
Architecture
Data Path Width 64
Cores per Chip 1
Threads per Core 1
Microarchitecture
µarch R10000
ISA
FP Pipe Stages 7
Int Pipe Stages 5
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 32
L1 Data Cache 32
L2 Cache
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache 4096
L3 Cache
Process Technology
Fabricated By NEC
Process http://cpudb.stanford.edu/technologies/83
Technology CMOS
Feature Size [μm] 0.35
Channel Length [μm] 0.35
Metal Layers 4
Metal Type
FO4 Delay [ps] 126.0

    Die Photo

    493

SpecInt1995

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11.1 9.8 10.7 11.1 10.7 10.0 11.7 10.9 source
11.0 9.8 10.5 10.4 10.6 9.2 11.6 9.7 source
10.2 10.4 9.9 11.4 10.1 9.6 11.0 8.8 source
11.1 9.8 10.7 11.1 10.7 10.0 11.7 10.9 source
11.0 9.8 10.5 10.4 10.6 9.2 11.6 9.7 source