| Microarchitecture | |
|---|---|
| µarch | EV6 |
| ISA | Alpha |
| FP Pipe Stages | 7 |
| Int Pipe Stages | 7 |
| Additional Specifications | |
|---|---|
| ISA Extensions | |
| Max µops (per-cycle) | 6 |
| IFU | 4 |
| LSFU | 2 |
| FPFU | 2 |
| TFU | 6 |
| Max Inst. Decoded | 4 |
| ROB Size | 80 |
| Inst. Window | 35 |
| IF Queue | 4 |
| Additional Specifications | |
|---|---|
| BHT Size | 29696 |
| BTB Size | 4096 |
| BP Acc | 0 |
| Registers (INT) | 39 |
| Registers (FP) | 31 |
| Registers (All) | |
| Memory BW [MB/s] | |
| Out of Order | true |
| Integrated Memory Ctrl | |
| Designer | Family | Code Name | Model | μarch | Released | Cache | Vdd | Feature Size | FO4 | Clock | TDP | SPECInt 1992 | SPECFp 1992 | SPECInt 1995 | SPECFp 1995 | SPECInt 2000 | SPECFp 2000 | SPECInt 2006 | SPECFp 2006 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DEC | Alpha 21264 | EV6 | EV6 | 1998-02-01 | 128 | 2.20 | 0.35 | 126.0 | 466.0 | 80.0 | 21.5 | 39.7 | details | |||||||
| DEC | Alpha 21264 | EV6 | EV6 | 1998-02-01 | 128 | 2.20 | 0.35 | 126.0 | 500.0 | 91.0 | 23.4 | 46.7 | 299.5 | 382.5 | details | |||||
| DEC | Alpha 21264 | EV6 | EV6 | 1998-02-01 | 128 | 2.20 | 0.35 | 126.0 | 525.0 | 95.0 | 24.1 | 36.0 | details | |||||||
| DEC | Alpha 21264 | EV6 | EV6 | 1998-02-01 | 128 | 2.20 | 0.35 | 126.0 | 575.0 | 100.0 | 25.9 | 39.7 | details |