Intel P6:Yonah µarch

Microarchitecture
µarch P6:Yonah
ISA x86-32
FP Pipe Stages
Int Pipe Stages 12
Additional Specifications
ISA Extensions SSE3
Max µops (per-cycle) 5
IFU
LSFU
FPFU
TFU
Max Inst. Decoded 3
ROB Size 80
Inst. Window 24
IF Queue
Additional Specifications
BHT Size
BTB Size
BP Acc
Registers (INT)
Registers (FP)
Registers (All)
Memory BW [MB/s]
Out of Order true
Integrated Memory Ctrl false

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
Intel Core Duo Yonah T2500 P6:Yonah 2048 0.065 11.4 2000.0 10.1 8.9 details
Intel Core Yonah T2300 P6:Yonah 2048 1.23 0.065 11.3 1660.0 31.0 details
Intel Core Yonah T2400 P6:Yonah 2006-01-01 2048 1.23 0.065 11.3 1830.0 31.0 details
Intel Core Yonah T2700 P6:Yonah 2006-06-01 2048 1.23 0.065 11.3 2330.0 31.0 details
Intel Core Yonah T2600 P6:Yonah 2006-01-01 2048 1.23 0.065 11.3 2160.0 31.0 details