MIPS R10000
T5, 180.0 MHz
| Specifications | |
|---|---|
| Designer | MIPS |
| Family | R10000 |
| Model | |
| Code Name | T5 |
| Clock [MHz] | 180.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 3.30 |
| TDP [W] | |
| Die Size [mm²] | 298 |
| Transistor [M] | 6.8 |
| Architecture | |
|---|---|
| Data Path Width | 64 |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Microarchitecture | |
|---|---|
| µarch | R10000 |
| ISA | |
| FP Pipe Stages | 7 |
| Int Pipe Stages | 5 |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | 32 |
| L1 Data Cache | 32 |
| L2 Cache | |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | 2048 |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | NEC |
| Process | http://cpudb.stanford.edu/technologies/83 |
| Technology | CMOS |
| Feature Size [μm] | 0.35 |
| Channel Length [μm] | 0.35 |
| Metal Layers | 4 |
| Metal Type | |
| FO4 Delay [ps] | 126.0 |
