CPU DB

MIPS R5000 µarch

Microarchitecture
µarch R5000
ISA
FP Pipe Stages
Int Pipe Stages 5
Additional Specifications
ISA Extensions
Max µops (per-cycle) 2
IFU 1
LSFU 1
FPFU 1
TFU 3
Max Inst. Decoded 2
ROB Size
Inst. Window 2
IF Queue
Additional Specifications
BHT Size
BTB Size
BP Acc
Registers (INT) 32
Registers (FP) 32
Registers (All) 64
Memory BW [MB/s]
Out of Order false
Integrated Memory Ctrl false

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
MIPS R5000 R5000 1996-01-01 512 3.30 0.35 126.0 150.0 3.3 4.4 details
MIPS R5000 R5000 1996-01-01 512 3.30 0.35 126.0 180.0 4.6 4.9 details
MIPS R5000 R5000 1996-01-01 64 3.30 0.35 126.0 200.0 5.7 details
MIPS R5000 R5000 1996-01-01 64 3.30 0.35 126.0 250.0 6.6 details