| Specifications | |
|---|---|
| Designer | Sun |
| Family | UltraSPARC IIIi |
| Model | |
| Code Name | Jalepeno |
| Clock [MHz] | 1336.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 1.30 |
| TDP [W] | 52.0 |
| Die Size [mm²] | 206 |
| Transistor [M] | 87.5 |
| Architecture | |
|---|---|
| Data Path Width | 64 |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | 32 |
| L1 Data Cache | 64 |
| L2 Cache | 1024 |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | TI |
| Process | http://cpudb.stanford.edu/technologies/103 |
| Technology | CMOS |
| Feature Size [μm] | 0.13 |
| Channel Length [μm] | |
| Metal Layers | 7 |
| Metal Type | copper |
| FO4 Delay [ps] | 25.2 |