Specifications | |
---|---|
Designer | Sun |
Family | UltraSPARC III Cu |
Model | |
Code Name | Cheetah+ |
Clock [MHz] | 1050.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
---|---|
Voltage (Nom.) [V] | 1.60 |
TDP [W] | 80.0 |
Die Size [mm²] | 232 |
Transistor [M] | 29.0 |
Architecture | |
---|---|
Data Path Width | 64 |
Cores per Chip | 1 |
Threads per Core | 1 |
Cache (on-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | 32 |
L1 Data Cache | 64 |
L2 Cache | |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | 8192 |
L3 Cache |
Process Technology | |
---|---|
Fabricated By | TI |
Process | http://cpudb.stanford.edu/technologies/103 |
Technology | CMOS |
Feature Size [μm] | 0.13 |
Channel Length [μm] | |
Metal Layers | 7 |
Metal Type | copper |
FO4 Delay [ps] | 25.2 |
Gzip | Vpr | Gcc | Mcf | Crafty | Parser | Eon | Perlbmk | Gap | Vortex | Bzip2 | Twolf | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
433.0 | 460.0 | 577.0 | 659.0 | 558.0 | 488.0 | 527.0 | 540.0 | 372.0 | 738.0 | 629.0 | 570.0 | source |
417.0 | 474.0 | 586.0 | 588.0 | 577.0 | 496.0 | 670.0 | 555.0 | 404.0 | 859.0 | 606.0 | 572.0 | source |
416.0 | 473.0 | 598.0 | 600.0 | 582.0 | 500.0 | 675.0 | 561.0 | 404.0 | 862.0 | 609.0 | 575.0 | source |
Wupwise | Swim | Mgrid | Applu | Mesa | Galgel | Art | Equake | Facerec | Ammp | Lucas | Fma3d | Sixtrack | Apsi | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
660.0 | 944.0 | 479.0 | 332.0 | 573.0 | 1655.0 | 9713.0 | 651.0 | 908.0 | 505.0 | 385.0 | 402.0 | 361.0 | 556.0 | source |
659.0 | 980.0 | 487.0 | 310.0 | 543.0 | 1713.0 | 9389.0 | 645.0 | 958.0 | 509.0 | 371.0 | 400.0 | 366.0 | 471.0 | source |
777.0 | 949.0 | 625.0 | 643.0 | 607.0 | 1725.0 | 8760.0 | 1342.0 | 1038.0 | 512.0 | 474.0 | 421.0 | 311.0 | 570.0 | source |
787.0 | 999.0 | 636.0 | 644.0 | 615.0 | 1744.0 | 8766.0 | 1337.0 | 1060.0 | 521.0 | 470.0 | 433.0 | 358.0 | 578.0 | source |