CPU DB

Intel Core 2 Extreme X9000

Penryn, 2800.0 MHz

Specifications
Designer Intel
Family Core 2 Extreme
Model X9000
Code Name Penryn
Clock [MHz] 2800.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V] 1.14
TDP [W] 44.0
Die Size [mm²] 107
Transistor [M] 410.0
Architecture
Data Path Width 64
Cores per Chip 2
Threads per Core 1
Microarchitecture
µarch Core:Penryn
ISA x86-64
FP Pipe Stages
Int Pipe Stages 14
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 32
L1 Data Cache 32
L2 Cache 6144
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache
L3 Cache
Process Technology
Fabricated By Intel
Process http://cpudb.stanford.edu/technologies/61
Technology CMOS
Feature Size [μm] 0.045
Channel Length [μm] 0.035
Metal Layers 9
Metal Type copper
FO4 Delay [ps] 12.6

    SpecInt2006

    Perlbench Bzip2 Gcc Mcf Gobmk Hmmer Sjeng Libquantum H264ref Omnetpp Astar Xalancbmk
    18.1 15.1 12.1 25.5 17.7 14.6 16.8 33.0 29.1 14.4 14.1 20.1 source
    17.2 15.3 19.0 25.5 18.4 14.7 16.9 32.5 28.9 15.7 14.3 21.5 source
    17.6 15.2 17.5 25.4 17.7 14.7 16.9 31.3 28.9 15.6 14.2 20.9 source

    SpecFp2006

    Bwaves Gamess Milc Zeusmp Gromacs Cactusadm Leslie3d Namd Dealii Soplex Povray Calculix Gemsfdtd Tonto Lbm Wrf Sphinx3
    23.6 19.9 10.9 18.0 18.1 24.0 15.4 14.6 15.3 14.7 21.2 14.0 12.9 18.1 17.6 21.0 26.7 source
    23.8 20.0 10.9 18.2 18.4 24.6 15.5 14.6 15.8 14.8 21.5 14.2 13.1 19.5 17.7 21.2 26.9 source
    22.5 17.0 10.7 17.4 16.8 23.5 14.4 14.5 17.4 14.5 20.6 12.7 12.1 16.8 16.9 19.2 27.5 source