Specifications | |
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Designer | AMD |
Family | Athlon |
Model | 900 |
Code Name | Pluto |
Clock [MHz] | 900.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
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Voltage (Nom.) [V] | |
TDP [W] | |
Die Size [mm²] | |
Transistor [M] |
Architecture | |
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Data Path Width | |
Cores per Chip | 1 |
Threads per Core | 1 |
Microarchitecture | |
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µarch | K75 |
ISA | |
FP Pipe Stages | |
Int Pipe Stages |
Cache (on-chip) | |
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L1 Unified Cache | |
L1 Instruction Cache | 64 |
L1 Data Cache | 64 |
L2 Cache | 512 |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |
Process Technology | |
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Fabricated By | AMD |
Process | http://cpudb.stanford.edu/technologies/5 |
Technology | CMOS |
Feature Size [μm] | 0.18 |
Channel Length [μm] | 0.1 |
Metal Layers | |
Metal Type | |
FO4 Delay [ps] | 36.0 |