Specifications | |
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Designer | Intel |
Family | Atom |
Model | D525 |
Code Name | Pineview |
Clock [MHz] | 1800.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
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Voltage (Nom.) [V] | 0.99 |
TDP [W] | 13.0 |
Die Size [mm²] | |
Transistor [M] |
Architecture | |
---|---|
Data Path Width | |
Cores per Chip | 2 |
Threads per Core | 2 |
Cache (on-chip) | |
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L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | 1022 |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |
Process Technology | |
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Fabricated By | Intel |
Process | http://cpudb.stanford.edu/technologies/61 |
Technology | CMOS |
Feature Size [μm] | 0.045 |
Channel Length [μm] | 0.035 |
Metal Layers | 9 |
Metal Type | copper |
FO4 Delay [ps] | 12.6 |
Gzip | Vpr | Gcc | Mcf | Crafty | Parser | Eon | Perlbmk | Gap | Vortex | Bzip2 | Twolf | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
607.0 | 423.0 | 985.0 | 758.0 | 659.0 | 679.0 | 881.0 | 867.0 | 843.0 | 1215.0 | 541.0 | 582.0 | source |