CPU DB

Zilog Z8000

MHz

Specifications
Designer Zilog
Family Z8000
Model
Code Name
Clock [MHz]
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V]
TDP [W]
Die Size [mm²]
Transistor [M]
Architecture
Data Path Width 16
Cores per Chip 1
Threads per Core 1
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache
L3 Cache