Specifications | |
---|---|
Designer | Sun |
Family | SuperSPARC I |
Model | |
Code Name | Viking |
Clock [MHz] | 60.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
---|---|
Voltage (Nom.) [V] | 5.00 |
TDP [W] | 14.2 |
Die Size [mm²] | 256 |
Transistor [M] | 3.1 |
Architecture | |
---|---|
Data Path Width | 32 |
Cores per Chip | 1 |
Threads per Core | 1 |
Microarchitecture | |
---|---|
µarch | SuperSPARC I |
ISA | |
FP Pipe Stages | 4 |
Int Pipe Stages | 4 |
Cache (on-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | 20 |
L1 Data Cache | 16 |
L2 Cache | |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | 1024 |
L3 Cache |
Process Technology | |
---|---|
Fabricated By | TI |
Process | http://cpudb.stanford.edu/technologies/92 |
Technology | BICMOS |
Feature Size [μm] | 0.8 |
Channel Length [μm] | 0.8 |
Metal Layers | 2 |
Metal Type | |
FO4 Delay [ps] | 288.0 |
Espresso | Li | Eqntott | Compress | Sc | Gcc | |
---|---|---|---|---|---|---|
74.4 | 73.8 | 119.6 | 49.5 | 108.4 | 57.6 | source |
74.7 | 90.0 | 122.2 | 50.0 | 108.4 | 69.8 | source |
Spice2g6 | Doduc | Mdljdp2 | Wave5 | Tomcatv | Ora | Alvinn | Ear | Mdljsp2 | Swm256 | Su2cor | Hydro2d | Nasa7 | Fpppp | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
58.1 | 73.2 | 96.6 | 70.3 | 93.0 | 182.3 | 207.8 | 105.8 | 48.0 | 50.6 | 108.7 | 101.4 | 78.1 | 111.8 | source |
69.5 | 102.8 | 105.5 | 68.4 | 94.0 | 172.2 | 135.1 | 111.2 | 49.9 | 52.6 | 130.4 | 98.8 | 113.1 | 114.4 | source |
58.8 | 75.3 | 98.7 | 83.9 | 148.0 | 183.2 | 211.3 | 108.0 | 48.6 | 94.9 | 191.4 | 175.4 | 109.8 | 111.7 | source |
58.8 | 75.3 | 98.7 | 83.9 | 148.0 | 183.2 | 211.3 | 108.0 | 48.6 | 94.9 | 191.4 | 175.4 | 109.8 | 111.7 | source |