Specifications | |
---|---|
Designer | Sun |
Family | SuperSPARC I |
Model | |
Code Name | Viking |
Clock [MHz] | 50.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
---|---|
Voltage (Nom.) [V] | 5.00 |
TDP [W] | |
Die Size [mm²] | 256 |
Transistor [M] | 3.1 |
Architecture | |
---|---|
Data Path Width | 32 |
Cores per Chip | 1 |
Threads per Core | 1 |
Microarchitecture | |
---|---|
µarch | SuperSPARC I |
ISA | |
FP Pipe Stages | 4 |
Int Pipe Stages | 4 |
Cache (on-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | 20 |
L1 Data Cache | 16 |
L2 Cache | |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | 1024 |
L3 Cache |
Process Technology | |
---|---|
Fabricated By | TI |
Process | http://cpudb.stanford.edu/technologies/92 |
Technology | BICMOS |
Feature Size [μm] | 0.8 |
Channel Length [μm] | 0.8 |
Metal Layers | 2 |
Metal Type | |
FO4 Delay [ps] | 288.0 |
Espresso | Li | Eqntott | Compress | Sc | Gcc | |
---|---|---|---|---|---|---|
62.0 | 61.6 | 100.9 | 41.0 | 92.3 | 47.9 | source |
62.7 | 75.3 | 101.9 | 41.5 | 88.5 | 58.1 | source |
60.2 | 59.8 | 97.3 | 37.8 | 87.8 | 47.2 | source |
60.2 | 72.7 | 98.2 | 37.9 | 84.7 | 56.7 | source |
Spice2g6 | Doduc | Mdljdp2 | Wave5 | Tomcatv | Ora | Alvinn | Ear | Mdljsp2 | Swm256 | Su2cor | Hydro2d | Nasa7 | Fpppp | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
48.9 | 64.6 | 80.8 | 59.2 | 75.3 | 152.0 | 175.2 | 88.2 | 40.0 | 41.8 | 89.3 | 84.4 | 65.7 | 93.6 | source |
56.6 | 84.9 | 87.7 | 57.3 | 79.3 | 143.5 | 112.8 | 92.6 | 41.5 | 43.1 | 110.0 | 84.1 | 83.6 | 94.2 | source |
43.3 | 58.9 | 78.3 | 51.5 | 88.9 | 151.7 | 152.9 | 88.5 | 39.7 | 62.0 | 51.3 | 66.9 | 47.7 | 71.3 | source |
49.4 | 75.6 | 84.2 | 50.3 | 93.6 | 143.5 | 108.3 | 93.5 | 41.1 | 60.3 | 64.0 | 64.9 | 73.8 | 77.6 | source |