| Specifications | |
|---|---|
| Designer | Motorola |
| Family | 68000 |
| Model | |
| Code Name | |
| Clock [MHz] | 14.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 5.00 |
| TDP [W] | |
| Die Size [mm²] | 44 |
| Transistor [M] | 0.068 |
| Architecture | |
|---|---|
| Data Path Width | 16 |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Microarchitecture | |
|---|---|
| µarch | 68000 |
| ISA | |
| FP Pipe Stages | |
| Int Pipe Stages | |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | Motorola |
| Process | http://cpudb.stanford.edu/technologies/79 |
| Technology | NMOS |
| Feature Size [μm] | 3.5 |
| Channel Length [μm] | 3.5 |
| Metal Layers | |
| Metal Type | |
| FO4 Delay [ps] | 1260.0 |
| Mips | |
|---|---|
| 0.7 | source hidden |