Specifications | |
---|---|
Designer | MOS |
Family | 6502 |
Model | |
Code Name | |
Clock [MHz] | 2.0 |
Max Clock (Turbo) [MHz] |
Physical Details | |
---|---|
Voltage (Nom.) [V] | |
TDP [W] | |
Die Size [mm²] | |
Transistor [M] | 0.00351 |
Architecture | |
---|---|
Data Path Width | 8 |
Cores per Chip | 1 |
Threads per Core | 1 |
Microarchitecture | |
---|---|
µarch | 6502 |
ISA | |
FP Pipe Stages | |
Int Pipe Stages |
Cache (on-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |