Specifications | |
---|---|
Designer | Intel |
Family | Xeon |
Model | EC5549 |
Code Name | Jasper Forest |
Clock [MHz] | 2533.0 |
Max Clock (Turbo) [MHz] | 2933.0 |
Physical Details | |
---|---|
Voltage (Nom.) [V] | 1.25 |
TDP [W] | 85.0 |
Die Size [mm²] | |
Transistor [M] |
Architecture | |
---|---|
Data Path Width | |
Cores per Chip | 4 |
Threads per Core | 2 |
Microarchitecture | |
---|---|
µarch | Nehalem |
ISA | x86-64 |
FP Pipe Stages | 16 |
Int Pipe Stages | 16 |
Cache (on-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | 32 |
L1 Data Cache | 32 |
L2 Cache | 1024 |
L3 Cache | 8192 |
Cache (off-chip) | |
---|---|
L1 Unified Cache | |
L1 Instruction Cache | |
L1 Data Cache | |
L2 Cache | |
L3 Cache |
Process Technology | |
---|---|
Fabricated By | Intel |
Process | http://cpudb.stanford.edu/technologies/61 |
Technology | CMOS |
Feature Size [μm] | 0.045 |
Channel Length [μm] | 0.035 |
Metal Layers | 9 |
Metal Type | copper |
FO4 Delay [ps] | 12.6 |
Application | Measured Power [W] |
---|---|
idle (+PM) | 22.0 |
idle (-PM) | 29.0 |
SpecInt2006 | 55.0 |
L3 fwd | 56.0 |
SpecFp2006 | 56.0 |
IPSec | 60.0 |
TDP Workload | 68.0 |