IBM
PowerPC 604ev
Mach 5,
350.0
MHz
|
Specifications
|
| Designer |
IBM |
| Family |
PowerPC 604ev |
| Model |
|
| Code Name |
Mach 5 |
| Clock [MHz] |
350.0 |
| Max Clock (Turbo) [MHz] |
|
|
Physical Details
|
| Voltage (Nom.) [V] |
1.90 |
| TDP [W] |
8.0 |
| Die Size [mm²] |
47 |
| Transistor [M] |
5.1 |
| Architecture |
| Data Path Width |
32 |
| Cores per Chip |
1 |
| Threads per Core |
1 |
| Cache (on-chip) |
| L1 Unified Cache |
|
| L1 Instruction Cache |
32 |
| L1 Data Cache |
32 |
| L2 Cache |
|
| L3 Cache |
|
| Cache (off-chip) |
| L1 Unified Cache |
|
| L1 Instruction Cache |
|
| L1 Data Cache |
|
| L2 Cache |
|
| L3 Cache |
|
| Process Technology |
| Fabricated By |
IBM |
| Process |
CMOS-6S2 |
| Technology |
CMOS |
| Feature Size [μm] |
0.25 |
| Channel Length [μm] |
0.18 |
| Metal Layers |
5 |
| Metal Type |
aluminum |
| FO4 Delay [ps] |
95.4
|