| Specifications | |
|---|---|
| Designer | IBM |
| Family | Power6 |
| Model | |
| Code Name | |
| Clock [MHz] | 5000.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 1.00 |
| TDP [W] | 160.0 |
| Die Size [mm²] | 341 |
| Transistor [M] | 790.0 |
| Architecture | |
|---|---|
| Data Path Width | 64 |
| Cores per Chip | 2 |
| Threads per Core | 2 |
| Microarchitecture | |
|---|---|
| µarch | Power6 |
| ISA | |
| FP Pipe Stages | 19 |
| Int Pipe Stages | 14 |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | 64 |
| L1 Data Cache | 64 |
| L2 Cache | 8192 |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | IBM |
| Process | http://cpudb.stanford.edu/technologies/36 |
| Technology | CMOS |
| Feature Size [μm] | 0.065 |
| Channel Length [μm] | 0.035 |
| Metal Layers | 10 |
| Metal Type | |
| FO4 Delay [ps] | 14.8 |