IBM Power2

P2SC, 77.0 MHz

Specifications
Designer IBM
Family Power2
Model
Code Name P2SC
Clock [MHz] 77.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V]
TDP [W]
Die Size [mm²] 335
Transistor [M] 15.0
Architecture
Data Path Width 32
Cores per Chip 1
Threads per Core 1
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 32
L1 Data Cache 256
L2 Cache
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache
L3 Cache
Process Technology
Fabricated By IBM
Process CMOS-6S
Technology CMOS
Feature Size [μm] 0.29
Channel Length [μm] 0.29
Metal Layers 5
Metal Type aluminum
FO4 Delay [ps] 104.4

    SpecInt1992

    EspressoLiEqntottCompressScGcc
    101.8 105.1 139.2 106.9 197.8 102.1 source

    SpecFp1992

    Spice2g6DoducMdljdp2Wave5TomcatvOraAlvinnEarMdljsp2Swm256Su2corHydro2dNasa7Fpppp
    142.1 175.5 262.6 169.7 473.2 228.3 662.9 416.7 84.2 240.1 589.0 269.7 278.6 347.2 source

    SpecInt1995

    GoM88ksimGccCompressLiIjpegPerlVortex
    4.9 2.7 3.8 4.9 3.0 4.3 3.1 3.4 source

    SpecFp1995

    TomcatvSwimSu2corHydro2dMgridAppluTurb3dApsiFppppWave5
    23.1 28.6 8.2 5.4 8.2 8.3 9.4 7.4 13.3 17.0 source
    23.1 28.6 8.2 5.4 8.2 8.3 9.4 7.4 13.3 17.0 source