| Specifications | |
|---|---|
| Designer | IBM |
| Family | Power2 |
| Model | |
| Code Name | Power2+ |
| Clock [MHz] | 67.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | |
| TDP [W] | |
| Die Size [mm²] | |
| Transistor [M] | |
| Architecture | |
|---|---|
| Data Path Width | 32 |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | 32 |
| L1 Data Cache | 64 |
| L2 Cache | 2048 |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | IBM |
| Process | http://cpudb.stanford.edu/technologies/42 |
| Technology | CMOS |
| Feature Size [μm] | 0.72 |
| Channel Length [μm] | 0.45 |
| Metal Layers | 4 |
| Metal Type | |
| FO4 Delay [ps] | 162.0 |