Fujitsu
SPARC64 GP
450.0
MHz
Specifications
|
Designer |
Fujitsu |
Family |
SPARC64 GP |
Model |
|
Code Name |
|
Clock [MHz] |
450.0 |
Max Clock (Turbo) [MHz] |
|
Physical Details
|
Voltage (Nom.) [V] |
1.90 |
TDP [W] |
21.0 |
Die Size [mm²] |
126 |
Transistor [M] |
|
Architecture |
Data Path Width |
64 |
Cores per Chip |
1 |
Threads per Core |
1 |
Cache (on-chip) |
L1 Unified Cache |
|
L1 Instruction Cache |
128 |
L1 Data Cache |
128 |
L2 Cache |
|
L3 Cache |
|
Cache (off-chip) |
L1 Unified Cache |
|
L1 Instruction Cache |
|
L1 Data Cache |
|
L2 Cache |
8192 |
L3 Cache |
|
Process Technology |
Fabricated By |
Fujitsu |
Process |
CS-80 |
Technology |
CMOS |
Feature Size [μm] |
0.18 |
Channel Length [μm] |
|
Metal Layers |
6 |
Metal Type |
copper |
FO4 Delay [ps] |
36.0
|
SpecInt2000
Gzip |
Vpr |
Gcc |
Mcf |
Crafty |
Parser |
Eon |
Perlbmk |
Gap |
Vortex |
Bzip2 |
Twolf |
|
274.0 |
264.0 |
203.0 |
329.0 |
305.0 |
300.0 |
318.0 |
317.0 |
192.0 |
458.0 |
294.0 |
262.0 |
source |
274.0 |
264.0 |
203.0 |
329.0 |
305.0 |
300.0 |
318.0 |
317.0 |
192.0 |
458.0 |
294.0 |
262.0 |
source |