CPU DB

AMD Phenom II 955

Deneb, 3200.0 MHz

Specifications
Designer AMD
Family Phenom II
Model 955
Code Name Deneb
Clock [MHz] 3200.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V] 1.13
TDP [W] 125.0
Die Size [mm²] 258
Transistor [M] 758.0
Architecture
Data Path Width 64
Cores per Chip 4
Threads per Core 1
Microarchitecture
µarch K10
ISA x86-64
FP Pipe Stages 17
Int Pipe Stages 12
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 64
L1 Data Cache 64
L2 Cache 2048
L3 Cache 6144
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache
L3 Cache
Process Technology
Fabricated By AMD
Process http://cpudb.stanford.edu/technologies/1
Technology CMOS
Feature Size [μm] 0.045
Channel Length [μm] 0.025
Metal Layers
Metal Type
FO4 Delay [ps] 9.0

    SpecInt2006

    Perlbench Bzip2 Gcc Mcf Gobmk Hmmer Sjeng Libquantum H264ref Omnetpp Astar Xalancbmk
    19.4 15.5 16.5 13.5 20.4 6.4 17.6 56.6 28.4 13.3 13.7 19.2 source
    20.3 15.7 14.5 19.1 21.3 20.8 18.5 233.0 34.9 15.2 16.1 18.1 source

    SpecFp2006

    Bwaves Gamess Milc Zeusmp Gromacs Cactusadm Leslie3d Namd Dealii Soplex Povray Calculix Gemsfdtd Tonto Lbm Wrf Sphinx3
    38.8 18.8 11.5 19.7 17.1 50.0 14.1 15.9 17.0 13.0 24.7 7.4 16.9 11.4 23.0 24.0 23.9 source
    53.4 21.5 30.8 48.0 18.3 86.5 31.7 16.8 23.4 15.3 23.8 25.0 25.6 19.8 65.1 32.6 28.7 source