| Specifications | |
|---|---|
| Designer | Intel |
| Family | Atom |
| Model | Z520 |
| Code Name | Silverthorne |
| Clock [MHz] | 1330.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 0.93 |
| TDP [W] | 2.0 |
| Die Size [mm²] | 26 |
| Transistor [M] | 47.0 |
| Architecture | |
|---|---|
| Data Path Width | 32 |
| Cores per Chip | 1 |
| Threads per Core | 2 |
| Microarchitecture | |
|---|---|
| µarch | Bonnel |
| ISA | |
| FP Pipe Stages | |
| Int Pipe Stages | |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | 32 |
| L1 Data Cache | 24 |
| L2 Cache | 512 |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | Intel |
| Process | http://cpudb.stanford.edu/technologies/61 |
| Technology | CMOS |
| Feature Size [μm] | 0.045 |
| Channel Length [μm] | 0.035 |
| Metal Layers | 9 |
| Metal Type | copper |
| FO4 Delay [ps] | 12.6 |