CPU DB

AMD K5 µarch

Microarchitecture
µarch K5
ISA x86-32
FP Pipe Stages
Int Pipe Stages 5
Additional Specifications
ISA Extensions
Max µops (per-cycle) 4
IFU 2
LSFU 2
FPFU 1
TFU 6
Max Inst. Decoded 4
ROB Size 16
Inst. Window 11
IF Queue
Additional Specifications
BHT Size 1024
BTB Size
BP Acc
Registers (INT)
Registers (FP)
Registers (All)
Memory BW [MB/s]
Out of Order true
Integrated Memory Ctrl false

Designer Family Code Name Model μarch Released Cache Vdd Feature Size FO4 Clock TDP SPECInt 1992 SPECFp 1992 SPECInt 1995 SPECFp 1995 SPECInt 2000 SPECFp 2000 SPECInt 2006 SPECFp 2006
AMD K5 SSA/5 K5 1996-03-27 10 3.52 0.5 180.0 75.0 details
AMD K5 SSA/5 K5 1996-03-27 10 3.52 0.5 180.0 90.0 11.0 details