Ross hyperSPARC

Colorado 2, 100.0 MHz

Specifications
Designer Ross
Family hyperSPARC
Model
Code Name Colorado 2
Clock [MHz] 100.0
Max Clock (Turbo) [MHz]
Physical Details
Voltage (Nom.) [V] 3.30
TDP [W]
Die Size [mm²] 327
Transistor [M] 1.5
Architecture
Data Path Width 32
Cores per Chip 1
Threads per Core 1
Cache (on-chip)
L1 Unified Cache
L1 Instruction Cache 8
L1 Data Cache 0
L2 Cache
L3 Cache
Cache (off-chip)
L1 Unified Cache
L1 Instruction Cache
L1 Data Cache
L2 Cache 256
L3 Cache
Process Technology
Fabricated By Fujitsu
Process http://cpudb.stanford.edu/technologies/19
Technology CMOS
Feature Size [μm] 0.5
Channel Length [μm] 0.5
Metal Layers 3
Metal Type
FO4 Delay [ps] 180.0

    SpecInt1992

    Espresso Li Eqntott Compress Sc Gcc
    95.0 106.9 139.2 52.8 125.8 75.9 source
    94.2 100.0 169.2 53.6 208.8 71.7 source

    SpecFp1992

    Spice2g6 Doduc Mdljdp2 Wave5 Tomcatv Ora Alvinn Ear Mdljsp2 Swm256 Su2cor Hydro2d Nasa7 Fpppp
    73.9 119.2 170.8 88.9 118.8 227.6 167.5 156.2 87.0 70.6 157.3 129.7 80.5 104.1 source
    64.5 114.1 162.6 87.1 112.3 244.1 276.6 172.4 83.1 67.2 150.0 137.0 70.4 103.1 source