| Specifications | |
|---|---|
| Designer | Cypress |
| Family | Cypress |
| Model | CY7C601 |
| Code Name | |
| Clock [MHz] | 40.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 5.00 |
| TDP [W] | 3.0 |
| Die Size [mm²] | 64 |
| Transistor [M] | 0.08 |
| Architecture | |
|---|---|
| Data Path Width | 32 |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Microarchitecture | |
|---|---|
| µarch | SPARC |
| ISA | |
| FP Pipe Stages | |
| Int Pipe Stages | |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |
| Process Technology | |
|---|---|
| Fabricated By | Cypress |
| Process | http://cpudb.stanford.edu/technologies/13 |
| Technology | CMOS |
| Feature Size [μm] | 0.8 |
| Channel Length [μm] | 0.8 |
| Metal Layers | 2 |
| Metal Type | |
| FO4 Delay [ps] | 288.0 |