| Specifications | |
|---|---|
| Designer | Intel |
| Family | Celeron |
| Model | |
| Code Name | Tualatin |
| Clock [MHz] | 1200.0 |
| Max Clock (Turbo) [MHz] | |
| Physical Details | |
|---|---|
| Voltage (Nom.) [V] | 1.50 |
| TDP [W] | 32.1 |
| Die Size [mm²] | 80 |
| Transistor [M] | 44.0 |
| Architecture | |
|---|---|
| Data Path Width | |
| Cores per Chip | 1 |
| Threads per Core | 1 |
| Cache (on-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | 256 |
| L3 Cache | |
| Cache (off-chip) | |
|---|---|
| L1 Unified Cache | |
| L1 Instruction Cache | |
| L1 Data Cache | |
| L2 Cache | |
| L3 Cache | |